D Priyanjana Pal — Personal Webpage
• Circuit Design • ESD • Reliability

Doctoral Researcher at KIT

Experienced Senior ESD Design Engineer at Global Foundries with a demonstrated history of working in the semiconductors industry and academic researcher with expertise in analog circuit design and optimzation using ML methods, reliability analysis, and robust circuit design.

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About

I am a Ph.D researcher with a background in analog/ESD and circuit reliability. I work on reliable analog circuit design and computing at Karlsruhe Institute of Technology, Germany with University of Patras and Pragmatic Semiconductors. Previously at Global Foundries, Bangalore, I focused on ESD circuit design and device modeling and enablement for advanced nodes.

Focus Areas
Circuit design, Design Automation, ESD, Reliability
Publications in
DATE, DAC, ICCAD, ESWEEK, ETS, IEEE TCAD, ACM TECS
Tools
Cadence Virtuoso, Layout XL, Calibre, Synopsys Design Compiler, Primetime, R, Conformal, Spectre, HSPICE, MATLAB, Python, EMX
Location
Karlsruhe, Germany

Experience

Research Assistant

KIT Logo
Karlsruhe Institute of Technology (KIT) — Dec 2022–Present
  • Lead research on circuit design, bespoke hardware-aware machine-learning classifers, reliability and robustness of analog and digital computing circuits.
  • Developed variation‑aware methods and fault‑tolerant design flows.
  • Mentored undergraduate and graduate students; coordinated collaborations with University of Patras, Arizona State University and Pragmatic Semiconductors.

Senior ESD Design and Enablement Engineer — ESD

GF Logo
GlobalFoundries, Bangalore — Jan 2020–Nov 2022
  • RF ESD Design: Designed mmWave-compatible ESD protection circuits, i.e., RF-diodes, ggNMOS, SCR-based clamps, and optimized performance using S-parameter model and EMX.
  • ESD Compact Modeling: Developed and validated compact models for LV, MV, and HV ESD devices (RF-Diodes, LDMOS, VPNPs, BiSCR, Switch FETs) across advanced nodes (130nm–22FDX).
  • Automation & QA: Built Python/R scripts for model validation, hardware correlation, and data processing across technologies.
  • Layout & Tape-out: Designed DC/RF test structures, performed LVS/PEX extraction, and conducted RF modeling.
  • Collaboration & Training: Mentored peers on compact modeling, simulation, and layout workflows.

Technical Projects

Analog Design

IITGn, KIT, January 01, 2019 — Present
  • Designed a three-stage OTA achieving stable gain (≈0.9 V/V) and output current (≈10.6 µA) across −20 °C to 185 °C, with reference voltage stability (0.5–0.8 V at VDD = 1–3 V) and robust PVT tolerance.
  • Designed a flexible LDO regulator with stable output voltage across wide PVT and thermal variations, and integrate structural BIST ensuring reliable operation.
  • Designed a pruned binary-search ADC design that reduces area by ~2× versus SOTA ADCs and ~5.4× versus flash ADCs, with ~5× transistor-count reduction through in-training optimization.
  • 3-bit Flash ADC Design: Resolution of 3 bits (8 quantization levels, LSB = Vref/8); Reference Voltage = 1 V (scalable up to 3 V); Architecture with 7 comparators, resistor-ladder reference, and thermometer-to-binary encoder; Single clock cycle conversion speed (fastest ADC type).
  • 3-bit Binary-Search ADC: Staged comparisons (Vref/2 → {3/4, 1/4}Vref → {7/8, 5/8, 3/8, 1/8}Vref) to resolve (A2, A1, A0); implemented using resistor ladder + enabled comparators + small control (T2–T7); verified in Cadence; LSB = Vref/8.
  • Low Dropout Regulator (LDO): Designed in SCL 180 nm technology for digital applications with 200 mV dropout (Vin 2 V → 1.8 V), 200 ns settling time, 10 μA quiescent current, and PSRR of –40 dB @ 1 MHz.
  • Bandgap Reference Circuit (BGR): Developed in SCL 180 nm with 1.8 V supply (tolerant up to 2.5 V), –40 °C to 125 °C temperature range, and ultra-low power dissipation of 50 μW.
  • Charge Pump: Designed a high-efficiency charge pump in SCL 180 nm for flash memory applications; addressed threshold voltage degradation due to the body effect, achieving improved power efficiency with minimal performance loss.

Memories

IITGn, KIT, June 01, 2019 — January, 2025
  • Developed a trim-circuitry based dynamic testing scheme for CIM resistive memories, enabling faster testing while maintaining high defect coverage.
  • SRAM cell & 16×16 array (UMC 28nm): Read/write simulation; DRC/LVS in Cadence.
  • Radiation‑Hardened cells (SCL 180nm): Compact layouts for 6T/8T, DICE, BISER, BCDMR; DRC, LVS, PEX with Calibre.

Standard Cell Characterization (FlexIC PDK)

KIT, April 01, 2024 — Aug, 2024

Performed timing, power, and noise characterization of standard cells and flip-flops using Cadence Liberate.

Generated complete .lib (timing/power/noise) and .v (behavioral Verilog) libraries for integration into digital design flows.

Ensured accuracy of delay/transition models across PVT corners to enable robust synthesis and STA.

Reliable Analog Computing

KIT, December 2022 -Present

Energy‑efficient adaptive analog spiking networks and neuromorphic computing implemented on printed/flexible substrates.

Adaptive fault‑endurance framework enabling robust ultra‑low‑cost printed circuits.

LDMOS Characterization

IITGn, June 01, 2019 — Aug, 2019

Measured I‑V on LDMOS wafers using Keysight 1500; extracted breakdown voltage and transconductance across DUTs.

Talks & Presentations

Publications

2025

Power-Constrained Printed Neuromorphic Hardware Training

DAC 2025

Design power-constrained analog neuromorphic circuit and optimise using augmented Lagrangian training framework that enforces task-specific power constraints while preserving accuracy and achieving efficient Pareto-optimal power–accuracy trade-offs.

SpikeSynth: Energy-Efficient Adaptive Analog Printed Spiking Neural Networks

ICCAD 2025

Analog printed SNN demonstrating energy-efficient operation with adaptive learning.

PRINT-SAFE: Printed Ultra-Low-Cost Electronic X-Design with Scalable Adaptive Fault Endurance

ESWEEK/CASES-Journal Track 2025

Co-design of fault-tolerant printed circuits with adaptive endurance at ultra-low cost.

Efficient Analog Error Correction for Printed Unary-Encoded Computing

IEEE TCAD 2025

Lightweight analog error-correction for unary-encoded computing in flexible/printed platforms.

2024

Neural Architecture Search for Highly Bespoke Robust Printed Neuromorphic Circuits

ICCAD 2024

Evolutionary NAS tailored to printed analog neuromorphic circuits; improves robustness under device/process variation.

A Dynamic Testing Scheme for Resistive-Based Computation-In-Memory Architectures

ASPDAC 2024

Design trim-circuitry and develop trim-circuitry based testing scheme for CIM memories that reduces test time while ensuring high defect coverage.

Fault Sensitivity Analysis of Printed Bespoke Multilayer Perceptron Classifiers

ETS 2024

Comprehensive fault-sensitivity evaluation across digital/analog realizations of printed MLPs.

On-sensor printed machine learning classification via bespoke adc and decision tree co-design

DATE 2024

Propose the design of fully customized binary search ADCs and a co-design framework with Decision Tree classifiers, enabling self-powered on-sensor printed classifiers

Analog Printed Spiking Neuromorphic Circuit

DATE 2024

Printed analog spiking building block toward low-cost neuromorphic processors.

2023

On-sensor printed machine learning classification via bespoke adc and decision tree co-design

NanoArch 2023

Introduce a temporal processing block with learnable filters, extending neuromorphic circuits to handle time-series data efficiently with near-RNN accuracy.

Power-Aware Training for Energy-Efficient Printed Neuromorphic Circuits

ICCAD 2024

Developed power-aware design methodology for neuromorphic circuits, achieving ~2× reduction in power while maintaining 95% classification accuracy

Education

PhD (Dr.-Ing.) in Computer Science and Engineering (ongoing) KIT Logo

Karlsruhe Institute of Technology (KIT) — 2022–Present

Thesis: Reliable Analog Computing for ultra-resource constrained edge intelligence.Graduation Summer-2026.

M.Tech in Electrical Engineering KIT Logo

Indian Institute of Technology Gandhinagar — 2018–2020

Thesis: Design and optimisation of high‑voltage drain‑extended FinFET transistors for analog SoC applications. Graduated 2020.

B.Tech in Electronics & Communication Engineering KIT Logo

National Institute of Technology (NIT) Agartala — 2014–2018

Thesis: Area-Power-Power Density Aware OR-XNOR Network Synthesis Based on Fixed Polarity Dual Reed-Muller Expansion (FPDRM). Graduated 2018.

Mentoring & Leadership

Graduate Supervision (KIT)

2023–Present
  • Master’s theses on spiking neuromophic circuits and computing systems.
  • STDP-based supervised learning techniques.
  • Project guidance on variation‑aware design and testing methodology.

PSE/TSE Project Supervision

2024–Present
  • Developed a University Chatbot under the PSE program, enabling automated Q&A and student support.
  • Implemented an LSTM-based music generation project to compose melodies using LLM and LSTM networks.

Labs

Analog & Reliability
  • Hands‑on chip-design labs with Cadence/measurement and layout automation.

Leadership

PRICOM Project Proposal (September 1st, 2022 -March 31, 2025)
  • Engaged with PragmatIC and IMEC to get access to their flexIC PDK and also with layout-automation collaboration.
  • Horizon EU project (PRICOM) coordination, report writing and proposal contributions.

Contact

Email: pal.priyanjana@gmail.com

Mobile: +49-15750799038

Google Scholar: Scholar Profile

LinkedIn: LinkedIn

Open to collaborations in analog/ESD circuit design and circuit reliability.

References

Prof. Mehdi B. Tahoori (Ph.D. Advisor)

Chair of Dependable Nano-Computing (CDNC)
Karlsruhe Institute of Technology (KIT)
mehdi.tahoori@kit.edu

Dr. Dattatreya Prabhu Rachakonda

ESD Team Manager
Global Foundries, Bangalore, India
dattatreyaprabhu.rachakonda@globalfoundries.com

Mr. Rakesh Kumar Pothal

Staff Design Engineer
Semtech, Hyderabad, India
rpothal@semtech.com

Dr. Sani R. Nassif

Visting Professor at KIT
CEO, Radyalis, Austin, TX, USA
srn@radyalis.com

Dr. Anindya Nath

Staff Engineer
IBM Research, Albany, NY, USA
anindya.nath@gmail.com

Additional references available upon request.